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ISL6597
PVCC
R HI1
BOOT
G
C GD
D
C DS
overcharging, exceeding the device rating. Low-profile
MOSFETs, such as Direct FETs and multi-SOURCE leads
devices (SO-8, LFPAK, PowerPAK), have low parasitic lead
inductances and are preferred.
Layout Considerations
R LO1
UGATE
R G1
R GI1
C GS
Q1
A good layout helps reduce the ringing on the switching
node (PHASE) and significantly lower the stress applied to
S
PHASE
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
C GD
the output drives. The following advice is meant to lead to an
optimized layout and performance:
? Keep decoupling loops (VCC-GND, PVCC-PGND and
BOOT-PHASE) short and wide, at least 25 mils. Avoid
using vias on decoupling components other than their
ground terminals, which should be on a copper plane with
at least two vias.
? Minimize trace inductance, especially on low-impedance
R HI2
LGATE
G
C DS
lines. All power traces (UGATE, PHASE, LGATE, PGND,
PVCC, VCC, GND) should be short and wide, at least 25
R LO2
GND
R G2
R GI2
C GS
S
Q2
mils. Try to place power traces on a single layer,
otherwise, two vias on interconnection are preferred
where possible. For no connection (NC) pins on the QFN
part, connect it to the adjacent net (LGATE2/PHASE2) can
reduce trace inductance.
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Application Information
MOSFET Selection
The parasitic inductances of the PCB and of the power
devices’ packaging (both upper and lower MOSFETs) can
cause serious ringing, exceeding absolute maximum rating
of the devices. The negative ringing at the edges of the
PHASE node could increase the bootstrap capacitor voltage
through the internal bootstrap diode, and in some cases, it
may overstress the upper MOSFET driver. Careful layout,
proper selection of MOSFETs and packaging can go a long
way toward minimizing such unwanted stress.
? Shorten all gate drive loops (UGATE-PHASE and LGATE-
PGND) and route them closely spaced.
? Minimize the inductance of the PHASE node. Ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
? Minimize the current loop of the output and input power
trains. Short the source connection of the lower MOSFET
to ground as close to the transistor pin as feasible. Input
capacitors (especially ceramic decoupling) should be
placed as close to the drain of upper and source of lower
MOSFETs as possible.
? Avoid routing relatively high impedance nodes (such as
PWM and ENABLE lines) close to high dV/dt UGATE and
PHASE nodes.
PVCC
BOOT
D
In addition, connecting the thermal pad of the QFN package
to the power ground through multiple vias is recommended.
This is to improve heat dissipation and allow the part to
achieve its full thermal potential.
R HI1
R LO1
UGATE
G
Q1
Upper MOSFET Self Turn-On Effects At Startup
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
R PH = 1 Ω to 2 Ω
S
PHASE
FIGURE 5. PHASE RESISTOR TO MINIMIZE SERIOUS
NEGATIVE PHASE SPIKE
The D 2 -PAK, or D-PAK packaged MOSFETs, have large
parasitic lead inductances and are not recommended unless
a phase resistor (R PH ), as shown in Figure 5, is
implemented to prevent the bootstrap capacitor from
8
dV/dt rate while the driver outputs are floating, due to the
self-coupling via the internal C GD of the MOSFET, the
UGATE could momentarily rise up to a level greater than the
threshold voltage of the MOSFET. This could potentially turn
on the upper switch and result in damaging inrush energy.
Therefore, if such a situation (when input bus powered up
before the bias of the controller and driver is ready) could
conceivably be encountered, it is a common practice to
place a resistor (R UGPH ) across the gate and source of the
FN9165.1
May 4, 2007
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